Vendor Introduction
PhaseLink Corporation is a fabless semiconductor company with its Headquarters, R&D, Engineering, Marketing and Sales in the Silicon Valley (Fremont, CA), and Logistics and Operations in Taipei. It is a leading edge high-technology company at the heart of broadband and wireless telecommunications and personal electronics applications. The Company's expertise resides in mixed signal integrated circuits for frequency control equipment. Through our proprietary technology, PhaseLink provides unequaled performance in frequency synthesis for the optical and gigabit speed telecommunication networks, while constant efforts for innovation and simplification also deliver affordable clock generation products for the personal electronics applications, from home electronics applications to portable and wireless systems.
| Part Number | Description | Doc |
|---|---|---|
| PL123-02N | Non-PLL Fan-out buffer, 0-200MHz, Fan-Out 1:2 |  |
| PL123-05 | ZDB with internal feedback, 10-134MHz, Fan-Out 1:5 | |
| PL123-09 | ZDB with internal feedback, 10-134MHz, Fan-Out 1:9 | |
| PL123-09N | Non-PLL Fan-out buffer, 0-134MHz, Fan-Out 1:9 | |
| PL123E-05 | High-performance ZDB, internal feedback, 10-220MHz, Fan-Out 1:5 | |
| PL123E-09 | High-performance ZDB, internal feedback, 10-220MHz, Fan-Out 1:9 | |
| PL123S-05 | Spread-compatible ZDB, internal feedback, 10-134MHz, Fan-Out 1:5 | |
| PL123S-09 | Spread-compatible ZDB, internal feedback, 10-134MHz, Fan-Out 1:9 | |
| PL580-35 | PhasorV^(TM) VCXO, input 19-40MHz, output 38-320MHz in LVPECL, LVDS or LVCMOS | |
| PL580-37 | PhasorV^(TM) VCXO, input 19-40MHz, output 38-320MHz in LVPECL, LVDS or LVCMOS | |
| PL580-38 | PhasorV^(TM) VCXO, input 19-40MHz, output 38-320MHz in LVPECL, LVDS or LVCMOS | |
| PL580-39 | PhasorV^(TM) VCXO, input 19-40MHz, output 38-320MHz in LVPECL, LVDS or LVCMOS | |
| PL580-68 | PhasorV^(TM) VCXO, input 20-40MHz, output 320-640MHz in LVPECL or LVDS | |
| PL580-69 | PhasorV^(TM) VCXO, input 20-40MHz, output 320-640MHz in LVPECL or LVDS | |
| PL602-21 | HCSL-compatible PCIE clock generator, input 25MHz, output 100MHz, low jitter | |
| PL602-22 | HCSL-compatible PCIE clock generator, input 25MHz, output 125MHz, low jitter | |
| PL602-23 | HCSL-compatible PCIE clock generator, input 25MHz, output 200MHz, low jitter | |
| PL602-26 | HCSL-compatible PCIE clock generator, input 25MHz, output 25MHz, low jitter | |
| PL602-27 | HCSL-compatible PCIE clock generator, input 25MHz, output 250MHz, low jitter | |
| PL611s-02 | Programmable Clock, PLL, input 10-200MHz, output ~200MHz in FSEL/PDB/OE | |
| PL611s-02/03 | Programmable Clock, PLL, input 10-200MHz, output ~200MHz in FSEL/PDB/OE | |
| PL611s-17 | Programmable Clock, PLL, input 1-200MHz, output ~125MHz in FSEL/PDB/OE | |
| PL611s-18 | Programmable Clock, PLL, input 0.01-200MHz, output 0.5kHz~125MHz in FSEL/PDB/OE | |
| PL613-01 | Programmable Clock, PLL, input 10-200MHz, output ~200MHz in LVCMOS | |
| PL613-05 | Programmable Clock, PLL, input 10-200MHz, output ~200MHz in LVCMOS | |
| PL671-01 | Programmable Clock, PLL, input 1-200MHz, output ~200MHz, EMI reduction | |
| PL671-02 | Programmable Clock, PLL, input 1-200MHz, output ~200MHz, EMI reduction | |
| PLL602-00 | XO Clock + PLL, input 12-15MHz, output 12-200MHz in LVCMOS (Hi-Drive) | |
| PLL602-30 | XO Clock + PLL, input 12-15MHz, output 0.75-800MHz in LVPECL, LVDS or LVCMOS | |
| PLL602-35 | XO Clock + PLL, input 12-15MHz, output 0.75-800MHz in LVPECL inverted OE | |
| PLL602-37 | XO Clock + PLL, input 12-15MHz, output 0.75-800MHz in LVCMOS | |
| PLL602-38 | XO Clock + PLL, input 12-15MHz, output 0.75-800MHz in LVPECL | |
| PLL602-39 | XO Clock + PLL, input 12-15MHz, output 0.75-800MHz in LVDS | |
| PLL620-00 | XO Clock + PLL, input 100-200MHz, output 100-800MHz in LVPECL, LVDS or LVCMOS | |
| PLL701-21 | Pin-programmable Clock, PLL+SST, input 24-200MHz, output 33-90MHz, EMI reduction | |
